Patent attributes
A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer. Thus, another software component can call and interact with the watchdog timer interface for a system event and view the watchdog timer interface as a watchdog timer (i.e., the operation of the hardware based timer is transparent).
