US Patent 7698482 Multiple data rates in integrated circuit device serial interface
Patent 7698482 was granted and assigned to Altera on April, 2010 by the United States Patent and Trademark Office.
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A serial interface for a programmable logic device supports a wide range of data rates by providing a first number of channels supporting a first range of data rates and a second number of channels supporting a second range of data rates. The first range of data rates is preferably lower than the second range of data rates and preferably the first number of channels is higher than the second number of channels which preferably is 1. For backward compatibility with existing devices, the first number of channels in each interface preferably is four. Each channel preferably includes a physical medium attachment module and a physical coding sublayer module. Each of the higher-speed channels in the second number of channels preferably also includes a clock management unit, while the lower-speed channels in the first number of channels preferably share one or more clock management units.
US Patent 07698482 Multiple data rates in integrated circuit device serial interface US Patent 7698482 Multiple data rates in integrated circuit device serial interface
US Patent 07698482 Multiple data rates in integrated circuit device serial interface
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