Patent attributes
Systems and methods of laying out integrated circuits are disclosed. During the layout stage of an integrated circuit device, a fixed, physical geometry is created of the parameterized cells (PCells) included in the integrated circuit schematic. The systems include a proxy engine configured to save to cache the geometries created during the layout stage such that the geometries need not be recomputed when the design is opened after a save to disk operation, during which geometries may otherwise be destroyed. The proxy engine may further be configured to delegate requests for the creation of geometries to other components of the integrated circuit design system. In addition, the proxy engine may be configured to perform customized evaluations of PCells, other than or in addition to caching and delegation.
