US Patent 7698676 Method and system for improving manufacturability of integrated devices

A method and system for improving the yield of integrated devices by adaptively selecting contact and via sizes is described. According to this invention, the drawn size of via holes in a design layout is selected based on its adjacent geometry objects. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias; selecting an appropriate via size based on the free space and proximity configuration to create a new design layout; and fabricate the new layout with proximity correction on the photomask such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances.