US Patent 7698679 Method and apparatus for automatic routing yield optimization

A method is provided for optimizing routing on a substrate such as an integrated circuit or printed circuit board. The method defines a plurality of parallel strips on an initial routing layout of conductors for a layer of an integrated circuit. Each conductor within each strip defines a brick. For each of the plurality of strips, a spacing between bricks and a brick thickness of each brick is adjusted as a function of i) a location of a brick in adjacent strips corresponding to the same conductor; ii) a desired brick thickness; and iii) a desired brick spacing.