US Patent 7700435 Method for fabricating deep trench DRAM array

A method for fabricating deep trench DRAM array is disclosed. A substrate having thereon a memory array area is provided. An array of deep trench patterns is formed in the memory array area. The deep trench (DT) capacitor patterns include first dummy DT patterns in a first column, second dummy DT patterns in a first row and a plurality of effective DT capacitor patterns. Each of the first dummy DT patterns has an extended width (W) along a first direction, which is greater than or equal to a photomask's shift tolerance. Each of the second dummy DT patterns has an extended length (L) along a second direction, which is greater than or equal to the photomask's shift tolerance. The first direction is normal to the second direction.