US Patent 7705411 MEMS-topped integrated circuit with a stress relief layer

Patent 7705411 was granted and assigned to National Semiconductor on April, 2010 by the United States Patent and Trademark Office.

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Patent

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Current Assignee

National Semiconductor

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7705411

Patent Inventor Names

Peter Johnson0

Peter Smeys0

Date of Patent

April 27, 2010

Patent Application Number

12082208

Date Filed

April 9, 2008

Patent Primary Examiner

‌

Ida M. Soward

Patent abstract

The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices.

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