Patent attributes
A method of testing power-on reset circuitry in an integrated circuit comprises establishing the a first state of the integrated circuit that is different from a normal reset state of the circuit, lowering the VCC power supply voltage from a normal high operating level VH to a specified lower level VP then raising it back to the normal high level, then determining whether or not the integrated circuit has assumed the reset state. The testing can repeated with a plurality of lower VCC levels VP and under a variety of operating conditions to characterize resetting parameters and to designate pass/fail results for individual chips. If an AC voltage detector is part of the power-on reset circuitry, then it can tested separately, and DC testing occurs with very slow ramp rates for lowering and raising the power supply voltage.
