US Patent 7710146 Hierarchical FPGA configuration

A system for configuring programmable logic devices includes a serial data bus, a first device to fan-out data signals on the serial data bus, a second device to fan-in data signals on the serial data bus, and a control device that uses the first device and the second device to configure the serial data bus. The system configures a set of programmable logic devices by using the control device to configure the serial data bus such that the set of programmable logic devices are in communication with the serial data bus, and by sending configuration information to the set of programmable logic devices. A method for configuring programmable logic devices includes configuring a first programmable logic device such that the first programmable logic device includes signaling logic to fan-out configuration information, and using the first programmable logic device to configure at least two secondary programmable logic devices in parallel using the signaling logic to fan-out configuration information.