US Patent 7712002 Test circuit for semiconductor integrated circuit

The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks. The SFF circuits hold test data which is sequentially supplied, supply the test data to the logic blocks and receive logic operation data generated from the logic blocks. The logic operation data may be sequentially supplied from the SFF circuits, on the basis of which performances of the logic blocks are examined.