US Patent 7724854 Synchronization methodology for systems employing data pull flow control

In one embodiment, a system comprises a signal source for generating a digital signal in response to a data pull signal; a digital-to-analog converter (DAC); a first plurality of shift registers for registering digital words of the digital signal before receipt by the DAC; a synchronizing logic element for generating the data pull signal, wherein the synchronizing logic element initially generates the data pull signal to cause the signal source to generate a number of data words, ceases communication of the data pull signal upon receipt of a mark signal, and resumes communication of the data pull signal upon receipt of a trigger signal; and a second plurality of shift registers for registering the mark signal before communication to the synchronizing logic element, wherein the first and second plurality of shift registers are enabled by the data pull signal.