Patent attributes
A dual clock interface for an integrated circuit is described. An integrated circuit includes interface circuitry. The interface circuitry has a hardwired logic block. The hardwired logic block has a clock divider circuit coupled to receive a user clock signal and a core clock signal for dividing the core clock signal responsive to a frequency of the user clock signal to provide a divided clock signal with edges aligned to the core clock signal. The divided clock signal has the frequency of the user clock signal and a phase relationship of the user clock signal. User-side logic is coupled to receive the divided clock signal for the controlled passing of information responsive to the divided clock signal. Core-side logic is coupled to receive the core clock signal for the controlled passing of information responsive to the core clock signal.
