Patent attributes
A load generating apparatus for applying a load on a bus of a test target system, has a mode setting register to which an operation mode is set, a data size register to which a data size of one data transfer is set, a register group to which a base address which is a first access target address, an address interval for every stride executed by a stride function, and a number of strides are set, and an access part configured to access a memory space within the test target system based on the data size set in the data size register and information set in the register group, depending on the operation mode set in the mode setting register. The access part includes a mechanism to change the access target address to the memory space at the address interval, and a mechanism to generate a data pattern depending on the address interval and the data size, with respect to the memory space of the access target.
