US Patent 7728388 Power semiconductor device

A power semiconductor device includes a P type silicon substrate; a deep N well in the P type silicon substrate; a P grade region in the deep N well; a P+ drain region in the P grade region; a first STI region in the P grade region; a second STI region in the P grade region, wherein the first and second STI region isolate the P+ drain region; a third STI region in the deep N well; a gate electrode overlying an area between the second and third STI regions and covering a portion of the second STI region; a gate dielectric layer between the gate electrode and the P type silicon substrate; a P well formed at one side of the third STI region; and a P+ source region in the P well.