US Patent 7730357 Integrated memory system
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Patent abstract
An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.
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Patent Inventor Names
Rino Micheloni0
Roberto Ravasio0
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US Patent 07730357 Integrated memory system US Patent 7730357 Integrated memory system
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Patent Number
07730357
Patent Number
7730357
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US Patent 07730357 Integrated memory system
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Is a
Patent jurisdiction
Patent number
07730357
Date of patent
June 1, 2010
Patent application number
10805182
Date Filed
March 19, 2004
Patent primary examiner
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