US Patent 7733168 Fully differential comparator and fully differential amplifier

A first to a fourth sampling switch (1a to 1d), a first to a fourth sampling capacitance (4 to 7), and a first and a second charge redistribution switch (2a, 2b) are provided on the input side of a differential amplifier (8). A first and a second reset switch (3a, 3b) are provided between inputs and outputs of the differential amplifier (8). A positive-polarity input signal voltage (Vinp), a negative-polarity comparison reference voltage (Vrefn), a positive-polarity comparison reference voltage (Vrefp), and a negative-polarity input signal voltage (Vinn) are applied via the first to fourth sampling switches (1a to 1d) to one ends of the first to fourth sampling capacitances (4 to 7), respectively. During a reset period, the reset of the differential amplifier (8) is released after sampling of the voltages. During a comparison period, the first and second charge redistribution switches (2a, 2b) are caused to be in a conduction state.