US Patent 7733683 Semiconductor memory device

Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned on, data retained in the sense amplifiers are capable of being written to the memory cells during the same time period substantially.