US Patent 7737791 Spread spectrum clocking in fractional-N PLL

In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.