US Patent 7737985 Pixel cache for 3D graphics circuitry

Apparatus are provided including device memory, hardware entities, a sub-image cell value cache, and a cache write operator. At least some of the hardware entities perform actions involving access to and use of the device memory. The hardware entities include 3D graphics circuitry to process, for ready display, 3D images from primitive objects. The cache is separate from the device memory, and is provided to hold data, including buffered sub-image cell values. The cache is connected to the 3D graphics circuitry so that pixel processing portions of the 3D graphics circuitry access the buffered sub-image cell values in the cache, in lieu of the pixel processing portions directly accessing the sub-image cell values in the device memory. The write operator writes the buffered sub-image cell values to the device memory under direction of a priority scheme. The priority scheme preserves in the cache border cell values bordering one or more primitive objects.