US Patent 7739564 Testing an integrated circuit using dedicated function pins

Testing an integrated circuit using dedicated function pins in a non-dedicated function test mode is described. In a first mode, a circuit block is activated for processing first information provided via dedicated function pins. In a second mode, the circuit block is deactivated. Control logic is coupled to receive state information from a state storing device and coupled to receive the first information and second information from the dedicated function pins. The control logic is configured to gate the second information for passage to programmable logic responsive to the state information being for the second mode. The control logic is configured to gate the first information to preclude passage to the programmable logic responsive to the state information being for the first mode.