US Patent 7739628 Synchronous to asynchronous logic conversion

Apparatus, systems, and methods may operate to generate a synchronous netlist from a synchronous circuit design representation, automatically substitute asynchronous components taken from an asynchronous standard cell component library for corresponding standard cell synchronous components in the synchronous netlist to form an asynchronous core, and convert the synchronous netlist to an asynchronous circuit design representation. Additional apparatus, systems, and methods are disclosed.