US Patent 7743288 Built-in at-speed bit error ratio tester
Patent 7743288 was granted and assigned to Altera on June, 2010 by the United States Patent and Trademark Office.
Is a
Current Assignee
Date Filed
June 1, 2005
0
Date of Patent
June 22, 2010
0
Patent Application Number
11142961
0
Patent Inventor Names
Shoujun Wang
0
Patent Jurisdiction
Patent Number
Patent Primary Examiner
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