Patent attributes
A cascading input structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks, and a self-timed vertical cascade chain. Each of the logic blocks has self-timed first and second inputs. The vertical cascade chain has a plurality of self-timed outputs, each of the self-timed outputs being coupled to a first self-timed input of a corresponding logic block in the column. In some embodiments, each logic block includes a multiply block having first and second self-timed inputs, where each output of the vertical cascade chain is coupled to the first input of the multiply block in the corresponding logic block. In some embodiments having a multiply block in the logic block, the inputs and output may not be self-timed.
