US Patent 7746109 Circuits for sharing self-timed logic

An exemplary circuit for implementing logic sharing in self-timed circuits includes a shared logic circuit, an input circuit, an output circuit, and a pipelined routing path. The shared logic circuit has first and second self-timed inputs and first and second self-timed outputs. The input circuit is coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal. The output circuit is coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected output being determined by the self-timed select signal. The pipelined routing path routes the self-timed enable signal from the input circuit to the output circuit.