US Patent 7746122 Input buffer for semiconductor memory apparatus

Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.