Patent attributes
A printed circuit board is provided which is capable of shortening intervals among core layer vias and suppressing high impedance. After the core layer vias each having a cylindrical conducting layer are formed so that conducting portions come into contact with one another, a punching process is performed along a symmetric axis of each of four core layer vias so that a through-hole of a specified diameter passes through a core board to form the core layer vias separated from one another and the through-hole is filled with an insulator and a punching process is performed along a central axis of the through-hole filled with the insulator so as to pass through the core board to form the through-hole having a diameter being shorter than that of the through-hole and the conducting layer is formed on an inside wall of the through-hole to form the core layer via.
