US Patent 7751995 Capacitance measurement method employing floating gate of semiconductor device

A capacitance measurement method employing a floating gate of a semiconductor device in a circuit having a MOSFET in which a drain is connected to a ground and a source and a gate are connected to each other, and a capacitor having a capacitance Cr connected to the gate, includes: obtaining a slope S from a relationship between voltage Vs of the source and a voltage Vf applied to the capacitor; setting a standard slope S0 as a y-intercept of a first-order linear equation obtained from a relationship between the slope S depending on the source current Is and the Vo(Is); and calculating a gate-to-drain overlap capacitance Cdgo of the MOSFET based on a capacitance Cr of the capacitor and the standard slop S0.