Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
July 6, 2010
Patent Application Number
10891339
Date Filed
July 14, 2004
Patent Primary Examiner
Patent abstract
A FIFO memory error circuit has a read pointer coupled to a FIFO memory. The read pointer has a logic high output once every FIFO memory cycle. A write pointer is coupled to the FIFO memory and has a logic high output once every FIFO memory cycle. An error detector has a first input coupled to the read pointer and a second input coupled to the write pointer.
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