US Patent 7752516 Semiconductor device and scan test method

A semiconductor device includes a clock signal separating circuit and a logic circuit. The clock signal separating circuit separates a clock signal into a first separation clock signal and a second separation clock signal and to supply the second separation clock signal to a test circuit. The logic circuit generates an output clock signal from the first separation clock signal and a first scan clock signal to the test circuit. A second scan clock signal is supplied to the test circuit.