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US Patent 7752588 Timing driven force directed placement flow
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Patent
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Date Filed
December 29, 2007
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Date of Patent
July 6, 2010
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Patent Application Number
11967180
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Patent Citations Received
US Patent 11694015 Signal routing between memory and memory controller
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US Patent 11893334 Method for optimizing floor plan for an integrated circuit
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US Patent 11853675 Method for optimizing floor plan for an integrated circuit
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Patent Inventor Names
Subhasis Bose
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
7752588
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Patent Primary Examiner
Paul Dinh
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