US Patent 7757044 Facilitating store reordering through cacheline marking

One embodiment of the present invention provides a system that facilitates store reordering through cacheline marking. During operation, the system receives a memory operation which is directed to a cacheline. Next, the system determines whether a thread which is performing the memory operation has set a store-mark for the cacheline. If the thread has set the store-mark for the cacheline, the system performs the memory operation. Otherwise, the system determines if the cacheline has been store-marked by another thread. If so, the system delays the memory operation. On the other hand, if the cacheline has not been store-marked by another thread, the system performs the memory operation.