Patent attributes
A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.
