US Patent 7760573 Semiconductor memory device and stress testing method thereof

A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.