Patent attributes
A flash memory device includes a plurality of block selection circuits and a plurality of memory blocks. The plurality of block selection circuits generate a block select signal in response to a plurality of decoded block address signals and a block control signal. The plurality of memory blocks are connected to global lines in response to the block select signal, and include a plurality of memory cell arrays performing an erase operation in response to a well bias. Each of the block selection circuits generates the block select signal in response to the block control signal regardless of the plurality of decoded block address signals, or selects the block select signal to select a corresponding memory block in response to the plurality of decoded block address signals.
