US Patent 7760804 Efficient use of a render cache

Image data is processed into first and second component pixel blocks, where each of the first blocks is associated with a respective one of the second blocks to define a combination pixel block. The first and second blocks are written to memory through a cache that is used as a write buffer. The cache is logically partitioned into a contiguous portion to store the first blocks and not any second blocks, and another contiguous portion to store the second blocks and not any first blocks. Other embodiments are also described and claimed.