US Patent 7760948 Parallel coefficient bit modeling

A coefficient labeling circuit arrangement for bitplane coding passes in embedded block coding. In one embodiment, a significance lookahead circuit generates lookahead significance states of coefficients in past, current, and future magnitude stripe slices of a code-block containing a plurality of coefficients. A plurality of context labeling circuits are coupled in parallel to the significance lookahead circuit. Each context labeling circuit is configured with a respective significance propagation pass circuit, a respective magnitude refinement pass circuit, and a respective cleanup pass circuit. Context labels are generated in parallel for all bits of the current magnitude stripe slice.