Patent attributes
A semiconductor integrated circuit comprises a test mode decision circuit which decides a normal operation mode or a test mode when having input a clock from a reset state and started an operation by using a scan enable signal that is used for a scan test, and retains a decision result until the decision result is reset; a scan enable mask circuit which disables the transmission of a scan enable signal to an internal scan circuit according to a decision result signal; and an access control unit which disables the access to the internal memory unit according to the decision result signal output from the test mode decision circuit. Furthermore, the semiconductor integrated circuit has a configuration of using the scan enable signal and the normal operation input signal in common.
