Patent attributes
A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure; bonding the first pre-polishing substructure to a jig such that a first surface of the first pre-polishing substructure faces the jig; forming a first substructure by polishing a second surface of the first pre-polishing substructure; bonding the second pre-polishing substructure to the first substructure such that a first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and forming a second substructure by polishing a second surface of the second pre-polishing substructure.
