Patent attributes
To provide a control method and a control program of a prober that are capable of enhancing throughput. Chips are tested in step S2. In step S3, when the counted number Y of conforming chips has reached a predetermined number of conforming chips X which constitutes conditions for testing, the process advances to step S10. In step S10, testing of wafers taking place at that time is interrupted, and this wafer is stored in an output cassette OC1. In a subsequent step S11, the subsequent wafer is tested, and stored in the output cassette OC2 (step S12). When all wafers have been tested, the process advances to step S14, and testing of the lot is completed. As a result, wafers that remain untested and wafers that have been tested stored separately in the input cassette and the output cassettes.
