Patent attributes
A timing recovery circuit capable of enhancing the reliability of timing recovery in a receiver apparatus in a communication system that employs the scheme of modulating the amplitude of a carrier wave. In the receiver apparatus which receives a transmitted signal created by modulating the amplitude of the carrier wave, and which comprises an AD converter for converting the received signal into a digital signal by sampling the received signal at an n-times oversampling rate, the timing recovery circuit which recovers a clock signal by extracting timing information from the output of the AD converter is constructed by containing therein a decimation filter for decimating the output of the AD converter down to an m-times oversampling rate (where 1<m<n), a phase difference information calculator for calculating the phase difference information from the output of the decimation filter; a loop filter for averaging the output of the phase difference information calculator, and an oscillator for generating, based on the output of the loop filter, a clock signal for controlling the sampling performed by the AD converter.
