A first path for directly inputting a control signal from the outside to a data signal processor and a second path for inputting a control signal generated by a bus interface to the data signal processor can be selectively switched by a switching portion. At the test time of a timing controller, the first path is selected by the switching portion so that the control signal is directly input to the data signal processor without being passed through the bus interface having a slow operation clock, and thus the timing controller can be reliably tested. At the normal use time, the second path is selected by the switching portion, thereby the control signal is input via the bus interface to various kinds of processors such as the data signal processor, and thus the normal operation can be reliably treated.