US Patent 7774535 Memory system and memory device

According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory device. The second memory device is configured to receive write data from the controller and transmit read data to the controller via a second data pin included in the second memory device. A redelivery module within the first memory device is configured to receive an address and a command output from the controller via a predetermined signal line, and output the address and the command to the second memory device via remaining first data pin.