US Patent 7783940 Apparatus for redundancy reconfiguration of faculty memories

A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN−1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk−1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.