US Patent 7786782 Method and apparatus for counter-based clock signal adaptation

A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.