Patent attributes
A multi-bit digital to analog converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analog output signal (Vout+/Vout−). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which the further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of the data bits, (ii) an equalization phase (P6a) in which the further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor. The equalization phase masks nonlinearities arising in switches (S2) and thereby improves harmonic distortion.
