US Patent 7787148 Dual printhead controller architecture having hidden slave

Dual printhead controller architecture includes a master central processor capable of being interfaced with a first printhead. A slave central processor is capable of being interfaced with a second printhead. Data transfer means is operatively connected between the master central processor and the slave central processor to permit communication between the master and slave central processors. A host link is operatively connected to the master central processor to permit the master central processor to receive page data from a host processor. The master central processor is configured so that the slave central processor is hidden from the host processor.