US Patent 7788565 Semiconductor integrated circuit

A semiconductor integrated circuit having a low maximum allowable operating frequency such as an analog circuit can be prevented from being destroyed during a scan test. When a scan test mode signal is “1”, output signals of a first AND circuit and a second AND circuit are fixed to a low level and an output of an OR circuit is fixed to a high level. Therefore, output signals of fourth through sixth flip-flops FF4-FF6 are not transferred to first through third analog circuits during the scan test. On the other hand, the output signals of the fourth through sixth flip-flops FF4-FF6 are transferred to the first through third analog circuits during a normal operation.