US Patent 7790517 Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device forms an N− diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N− diffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the N− diffusion layer directly under the gate electrode of the antifuse element stabilizes electrical connection between the gate electrode and the source/drain diffusion region even during writing with a low write voltage.