US Patent 7791393 Precision falling edge generator

A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.