Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Hideyuki Noda0
Katsumi Dosaka0
Kazunori Saitoh0
Kazutami Ariomoto0
Date of Patent
September 7, 2010
Patent Application Number
12213131
Date Filed
June 16, 2008
Patent Citations Received
...
Patent Primary Examiner
Patent abstract
A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.
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